250 n-channel logic level enhancement mode field effect transistor features 250v , 6a , r ds(on) =450m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-220f full-pak for through hole absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 30 v -pulsed i d 6 a i dm a drain-source diode forward current i s 6 a maximum power dissipation p d w operating and storage temperautre range t j ,t stg -50 to 150 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 3.3 65 /w c /w c ? @tc=25 c derate above 25 c 0.3 w/ c drain current-continuous s g d 1 nov. 2002 24 CEF08N2 to-220f s d g 38
CEF08N2 electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d = 250 a 250 v zero gate voltage drain current i dss v ds = 250v, v gs =0v 25 a gate-body leakage i gss v gs =30v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a 24 v drain-source on-state resistance r ds(on) v gs = 10v, i d =5.1a 450 m ? on-state drain current i d(on) v gs = 10v, v ds =10v 10 4.4 a s forward transconductance fs g v ds = 50v, i d = 5.1a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =25v, v gs =0v f =1.0mh z 630 p f 100 p f p f 40 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd = 125v, i d = 5.6a, v gs =10v, r gen =12 ? 19 ns ns ns ns 11 46 10 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =200v, i d = 5.6a, v gs =10v 33 nc nc nc 5 11 fall time 2 26 30 90 30 40
CEF08N2 parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =8.1a 0.9 1.5 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) c, capacitance (pf) i d , drain current (a) 3 0.1 1 2 4 6 10 8 25 c -55 c 150 c 1.v ds =40v 2.pulse test figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , r ds(on) , normalized -100 -50 0 50 100 200 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v gs =10v i d =5.1a 150 ciss coss crss 900 750 600 450 300 150 0 0 1020 304050 12 10 8 6 4 2 0 0123 4 5 6 v gs =10,9,8,7v v g s =5v v gs =6v v gs =4 v
CEF08N2 with temperature figure 6. breakdown voltage variation figure 5. gate threshold variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 4 -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a 1.30 1.20 1.10 1.0 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a 10 10 0 10 10 3 2 1 10 -1 10 0 10 1 t c =25 c single pulse tj=150 c 1 0 0 3 s r ds (on )li m i t dc 1ms 10 m s 10 0 m s 5 4 6 0 1 2 3 0 2 4 68 v ds =50v 20 10 0.1 1 0.4 0.6 0.8 1.2 1.0 v gs =0v 8 6 4 2 0 10 0 7 14 21 28 v ds =200v i d =5.6a
figure 11. switching test circuit figure 12. switching waveforms CEF08N2 t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l 5 10 -5 10 -4 10 -3 10 -2 10 -1 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 10 -3 10 -2 10 -1 10 0 10 1 10 0 single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5
|
